Popcount3
A “population count” circuit counts the number of ‘1’s in an input vector. Build a population count circuit for a 3-bit input vector.
Module Declaration
module top_module(
input [2:0] in,
output [1:0] out );
answer
module top_module(
input [2:0] in,
output [1:0] out );
assign out = in[0] + in[1] + in[2];
endmodule
Gatesv
You are given a four-bit input vector in[3:0]. We want to know some relationships between each bit and its neighbour:
out_both: Each bit of this output vector should indicate whether both the corresponding input bit and its neighbour to the left (higher index) are ‘1’. For example, out_both[2] should indicate if in[2] and in[3] are both 1. Since in[3] has no neighbour to the left, the answer is obvious so we don’t need to know out_both[3].
out_any: Each bit of this output vector should indicate whether any of the corresponding input bit and its neighbour to the right are ‘1’. For example, out_any[2] should indicate if either in[2] or in[1] are 1. Since in[0] has no neighbour to the right, the answer is obvious so we don’t need to know out_any[0].
out_different: Each bit of this output vector should indicate whether the corresponding input bit is different from its neighbour to the left. For example, out_different[2] should indicate if in[2] is different from in[3]. For this part, treat the vector as wrapping around, so in[3]’s neighbour to the left is in[0].
Module Declaration
module top_module(
input [3:0] in,
output [2:0] out_both,
output [3:1] out_any,
output [3:0] out_different );
answer
module top_module(
input [3:0] in,
output [2:0] out_both,
output [3:1] out_any,
output [3:0] out_different );
integer i;
always@(*)
begin
for(i=0;i<3;i=i+1)
begin
out_both[i] = in[i+1]&in[i];
out_any[i+1] = in[i+1]|in[i];
out_different[i] = in[i+1] ^ in[i];
end
end
assign out_different[3] = in[3]^in[0];
endmodule
Gatesv100
You are given a 100-bit input vector in[99:0]. We want to know some relationships between each bit and its neighbour:
out_both: Each bit of this output vector should indicate whether both the corresponding input bit and its neighbour to the left are ‘1’. For example, out_both[98] should indicate if in[98] and in[99] are both 1. Since in[99] has no neighbour to the left, the answer is obvious so we don’t need to know out_both[99].
out_any: Each bit of this output vector should indicate whether any of the corresponding input bit and its neighbour to the right are ‘1’. For example, out_any[2] should indicate if either in[2] or in[1] are 1. Since in[0] has no neighbour to the right, the answer is obvious so we don’t need to know out_any[0].
out_different: Each bit of this output vector should indicate whether the corresponding input bit is different from its neighbour to the left. For example, out_different[98] should indicate if in[98] is different from in[99]. For this part, treat the vector as wrapping around, so in[99]’s neighbour to the left is in[0].
Module Declaration
module top_module(
input [99:0] in,
output [98:0] out_both,
output [99:1] out_any,
output [99:0] out_different );
answer
module top_module(
input [99:0] in,
output [98:0] out_both,
output [99:1] out_any,
output [99:0] out_different );
integer i;
always@(*)
begin
for(i=0;i<99; i=i+1)
begin
out_both[i] = in[i+1] & in[i];
out_any[i+1] = in[i+1] | in[i];
out_different[i] = in[i+1] ^ in[i];
end
end
assign out_different[99] = in[99]^in[0];
endmodule
Mux2to1
Create a one-bit wide, 2-to-1 multiplexer. When sel=0, choose a. When sel=1, choose b.
Expected solution length: Around 1 line.
Module Declaration
module top_module(
input a, b, sel,
output out );
answer
module top_module(
input a, b, sel,
output out );
assign out = (sel == 0 ? a : b);
endmodule
Mux2to1v
Create a 100-bit wide, 2-to-1 multiplexer. When sel=0, choose a. When sel=1, choose b.
Expected solution length: Around 1 line.
Module Declaration
module top_module(
input [99:0] a, b,
input sel,
output [99:0] out );
answer
module top_module(
input [99:0] a, b,
input sel,
output [99:0] out );
assign out = (sel == 0 ? a : b);
endmodule
Mux9to1v
Create a 16-bit wide, 9-to-1 multiplexer. sel=0 chooses a, sel=1 chooses b, etc. For the unused cases (sel=9 to 15), set all output bits to ‘1’.
Expected solution length: Around 15 lines.
Module Declaration
module top_module(
input [15:0] a, b, c, d, e, f, g, h, i,
input [3:0] sel,
output [15:0] out );
answer
module top_module(
input [15:0] a, b, c, d, e, f, g, h, i,
input [3:0] sel,
output [15:0] out );
assign out = (sel == 0) ? a :
(sel == 1) ? b :
(sel == 2) ? c :
(sel == 3) ? d :
(sel == 4) ? e :
(sel == 5) ? f :
(sel == 6) ? g :
(sel == 7) ? h :
(sel == 8) ? i : 16'hFFFF;
endmodule
Mux254to1
Create a 1-bit wide, 256-to-1 multiplexer. The 256 inputs are all packed into a single 256-bit input vector. sel=0 should select in[0], sel=1 selects bits in[1], sel=2 selects bits in[2], etc.
Expected solution length: Around 1 line.
Module Declaration
module top_module(
input [255:0] in,
input [7:0] sel,
output out );
answer
module top_module(
input [255:0] in,
input [7:0] sel,
output out );
assign out = in[sel];
endmodule
